An increasing portion of digital devices nowadays is based on multi-core CPUs. Besides consumer gear like smart phones, tablet PCs, game consoles, (smart) TVs etc. multi-core CPU comprising devices are the groundwork in particular for modern automotive, aerospace and industrial control applications. To provide high data access rates each core of a typical CPU is equipped with a fast private (L1) cache. All cores commonly share the comparably slow main memory (and L2 cache). To avoid data inconsistencies due to multiple write accesses the cache controllers implement cache coherence protocols. However, the communication Overhead increases with the number of CPU cores. This leads to an increase of the necessary chip area as well as to an increase of power consumption. Furthermore automotive, aerospace and industrial control applications demand hard real-time abilities. But the known cache coherence arrangements hardly provide this hard real-time functionality. All in all permanently increasing demands concerning processing speed, battery operation time, chip miniaturization level and particularly hard real-time constraints challenge the developers to offer a simple and reliable solution. The novel approach to meet this market demand is the On-demand Coherent Cache (ODC²) recently developed at the Robotics Research Institute of the TU Dortmund University.
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