A case study by researchers in the Center for Nanoscale Science and Engineering (CNSE) at North Dakota State University was published in the July 2008 issue of the Chip Scale Review magazine.
“Case Study: Building a Two-Chip Stacked Package” is authored by Fred Haring, research technician; Chris Hoffarth, engineering technician; Syed Sajid Ahmad, manager of engineering services; John Jacobson, senior design engineer; and Aaron Reinholz, associate director of electronics technology. CNSE staff members Linda Leick, Darci Hansen, Matt Sharpe and Meridith Bell also contributed significantly to the project.
With the increasing demand for more functionality and smaller size with portable devices such as cell phones, mp3 players, and GPS units, the performance and size of individual electronic components have become critical. The case study details how CNSE researchers design and manufacture a chip scale package. Engineering a single package housing multiple chips stacked vertically one on top of the other results in smaller and more efficient packages for devices. For example, CNSE researchers have successfully reduced the size of two electronics components by 75 percent.
Two or more processors packaged in a single package will result in an overall package size smaller than each individual package, yet will have the combined computing power of the two individual integrated processors. The case study walks through this two-chip stacked package process at CNSE, discussing stacked-die design considerations, substrate limitations, stack configuration, assembly process, process documentation, wire bonding, laser marking, ball attaching, singulation, inspection, testing, and hallmark successes of system completion.
The case study is found at http://www.chipscalereview.com/issues/0708/index.phpAbout the NDSU authors
Chris Hoffarth received his associate’s degree in electronics technology from North Dakota State College of Science, Wahpeton, N.D. Hoffarth was a surface mount technician at Vancsco Electronics in Valley City, N.D., before joining CNSE at NDSU in 2005. He manages the surface mount technology and chip scale package lines.
Syed Sajid Ahmad received his master’s degree in experimental physics from the University of the Punjab and his master’s degree in theoretical physics from Islamabad University, Pakistan. Ahmad was employed by Micron Technology conducting development and implementation of advanced packaging prior to joining CNSE at NDSU in 2003. At CNSE, he manages the research and manufacturing capabilities in the areas of thin film, thick film, chip scale packaging and surface mount technology.
John Jacobson received his bachelor’s degree in electronics technology from Arizona State University, Tempe. Prior to joining CNSE at NDSU in 2004, Jacobson served as a materials engineer at Micron Technology, Boise, Idaho. He leads design and electrical modeling of chip scale packaging efforts.
Aaron Reinholz received his bachelor’s degree in electrical engineering from NDSU. Prior to joining CNSE at NDSU in 2004, Reinholz served as an engineer at Rockwell Collins, Inc., Cedar Rapids, Iowa, for 13 years. He directs the CNSE engineering organization overseeing engineering services, coordinating industry partners, executing multiple projects and managing laboratory space. http://www.ndsu.edu/cnseAbout Chip Scale Review
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