IMEC realized full CMOS multiple antenna receiver for 60 GHz
At today’s IEEE International Solid State Circuit Conference, IMEC introduced its prototype of a 60GHz multiple antenna receiver, and invites industry to join its 60GHz research program.
The 60GHz band offers massive available bandwidth that enables very high bit rates of several Gbits-per-second at distances up to 10 meters (about 33 feet). To make the 60GHz technology cost-efficient to manufacture, low power and affordable in consumer products, IMEC has built its RF solution in a standard digital CMOS process thereby avoiding the extra cost of alternative technologies or dedicated RF process options.
The second industry goal is to overcome high path losses at mm-wave frequencies by using a phased antenna array approach. IMEC’s prototype uniquely addresses this problem by implementing a programmable phase shift of various incoming signals, which is necessary for beam-forming.
IMEC’s device contains two antenna paths, each consisting of a low-noise amplifier and a down-conversion mixer. The programmable phase shift is realized on the same chip. It starts from the quadrature signals of an on-chip quadrature voltage-controlled oscillator (QVCO). This QVCO design combines the highest oscillation frequency with the largest tuning range ever reported in CMOS.
IMEC’s multiple antenna receiver is the first step towards a complete CMOS-based phased array transceiver for 60GHz wireless personal area networks that envisage multi-gigabit-per-second applications such as fast kiosk downloading, wireless high-definition multimedia interface (HDMI), and other applications.
In the next phase of development, IMEC plans to implement four antenna paths using 45nm CMOS technology and to integrate other subsystems such as the phase-lock loop (PLL), analog-to-digital converter (ADC) and the patch-antenna array itself. IMEC will also begin initial experiments for a power amplifier.
These results were achieved in the unique multi-disciplinary 60GHz technology program. The research combines system-level aspects, algorithms, CMOS IC design, antenna design and module design, which target a low power 60 GHz communication link based on adaptive beamforming using multiple antennas aligned with ongoing standardization activities.
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