Next-Generation, High-bandwidth Memory Architecture Targets Communication Data Storage Applications
Infineon Technologies AG and Micron Technology, Inc., today announced the release of the complete specification for reduced latency DRAM II (RLDRAM™ II) architecture. Operating at speeds of up to 400 MHz, RLDRAM II products are the second-generation, ultra high-speed double data rate (DDR) SDRAM that combines fast random access with extremely high bandwidth and high density targeting communication and data storage applications. Datasheets for the 288Mb RLDRAM II devices are now available on the RLDRAM web site.
RLDRAM architecture is designed to meet the memory requirements of today’s high-bandwidth communication applications. The device’s eight-bank architecture is optimized for high speed and achieves a peak bandwidth of 28.8 gigabit per second (Gbps) using a 36-bit interface and a 400 MHz system clock. RLDRAM II boasts a low latency and random cycle time (tRC) of 20ns providing a higher data throughput. Additional advantages of the RLDRAM II feature set include; on-die termination (ODT), multiplexed or non-multiplexed addressing, on-chip delay lock loop (DLL), common or separate I/O and programmable output impedance and a power efficient 1.8V core. These features provide designers with increased design flexibility, balanced READ and WRITE ratio and the elimination of bus turnaround contention; as well as a simplified design-in process.
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