The FLAI platform incorporates two IMEC-proprietary ADRES (architecture for dynamically reconfigurable embedded systems) baseband processors fully supported by a proprietary C-code compiler, three digital front-end tiles with a proprietary ASIP (application-specific integrated processor) to assure sync-detection, an ARM™9 processor, and optimized AMBA™ interconnect to link the SoC’s modules with on-chip memories. The IP blocks come with reference platform control software and reference firmware for IEEE802.11n, 802.16e and 3GPP-LTE, as well as integration support.
Thanks to a patented platform control and power management approach, the SoC consumes only a few milliwatts in standby mode, yet is still capable of receiving an immediate burst from any supported wireless standard (reactive radio). When transmitting or receiving data bursts with multi-antenna encoding at more than 100Mbps, platform peak power is only 300mW.
IMEC also expects to combine its FLAI platform and flexible radio front-end (SCALDIO) in order to demonstrate a fully operational software-defined radio later this year. This platform achievement will be followed by a new generation of SDR research results, focusing on SDR and cognitive radio now under development. This new generation also includes a unified application-specific processor architecture that can reduce the area cost of implementing multi-mode advanced forward error correction.
FLAI Specifications•38 mm² die area
Katrien Marent | alfa
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