The threshold voltage variation (?Vt) of less than 40mV across wafer is also reported for 25nm gate length Fully Depleted SOI (FDSOI) devices using undoped channel and high-k and metal gates technology.
The work, carried out together with ST Microelectronics and SOITEC within the frame of the MEDEA+ DECISIF project, made use of the SOI process flow available in the CEA-LETI facilities in Grenoble. The device results indicated that the undoped channel FDSOI device with high-k/metal gate stack is a valid alternative to reduce variability issues at 22nm and below.
Comprehensive results of the influence of Si thickness, strain and process on the variability will be presented at the IEDM 2008 conference in December, where CEA-LETI will participate with over 10 papers on different aspects of nanotechnologies, advanced devices and process integration.
Leti operates with an annual budget of 174 M€ and employs 1,000 people with, in addition, more than 600 external collaborators (postgraduates, research and corporate partners). Leti has 8,000m² of clean rooms, an equipment portfolio worth 200 M€ and invests more than 40 M€ a year on new equipment. Leti has a dynamic Intellectual Property policy and has filed more than 200 new patent applications in 2007. Instigator of the MINATEC® pole of innovation, CEA Leti is also one of its principal partners, beside the Grenoble INP (Grenoble Institute of Technology) and the local authorities.
Clément Moulet | alfa
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