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Duolog Technologies announces the release of BitWise, its powerful SPIRIT compliant register management tool

Duolog Technologies, a leading provider of innovative Electronic System Level Design tools, today announced the release of BitWise, a high performance and flexible environment for capturing and generating register and memory map information for large SoCs. Duolog Technologies is headquartered in NovaUCD, the Innovation and Technology Transfer Centre in University College Dublin.

“Duolog has been busy with developing BitWise as part of the larger Socrates Framework,” commented Ray Bulger CEO, “Our open standards approach makes it easy to integrate our tool suite into any customer design flow. BitWise helps significantly reduce the number of design bugs, development cost and time to market for our customers.”

BitWise enables SoC verification and embedded SW tasks to take place concurrently. It provides SW engineers with an auto generated programmer’s manual that is in sync with the HW at all stages of the SoC development. The programmer’s manual contains all register and memory map information for the SoC. In addition, BitWise also provides automatically generated test-cases for the SoC verification and validation teams.

Loic Le Toumelin EDA Manager at TI France said “At TI we have been using Duolog’s fast track solutions for the past 3-4 years resulting in very significant reductions in SoC design times.” He added, “We are now transitioning over to BitWise and the Socrates framework and anticipate that our design cycle reductions will accelerate.”

BitWise accelerates the SoC design flow by allowing SoC Design/Verification and SW engineering teams to collaborate early on. The communication mechanism is through common intersection areas of both disciplines; SoC registers and memory maps. BitWise is an integral part of the SOCRATES framework, an SoC/IP capture and integration platform which utilises the IP-XACT 1.2 standard of the SPIRIT Consortium.

Miceal Whelan | alfa
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