Milestone to Fulfill Metallization Requirements for Chip Manufacturing into Next Decade
Infineon Technologies (FSE/NYSE: IFX) today announced that its Munich Research Labs have demonstrated, by shrinking present film thicknesses into nanotechnology geometries, that the stringent requirements of thin encapsulation films in metallization schemes of future chip generations will be met. The results shows that thin barrier films, key components for advanced copper chip wiring, will meet the electrical and functional demands defined for the end of the International Roadmap for Semiconductors (ITRS), which extends to 2016. The ITRS expects a reduction of the barrier thickness from 12nm (100nm node, 2003) to 2.5 nm (22 nm node, 2016). The goal of the Infineon researchers was to investigate the scaling limits of the current Ta /TaN barrier technology and its compatibility with the end-of-roadmap target values.
The Infineon researchers have successfully performed an electrical assessment of the integration of ultrathin metallic barrier films encapsulating copper metal lines in advanced chip metallization systems. These electrically conducting films separate the copper metal lines from the surrounding dielectrics used for electrical isolation. Hermetic encapsulation of copper lines has to prevent copper diffusion into the dielectric isolation, and in particular from reaching the transistors below the wiring layers in the chip, as at transistor level copper is readily destroying device operation.
Reiner Schoenrock | Infineon Technologies AG
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