Low background noise typically translates to better performance in electronics, such as longer ranges and clearer signals or higher information-carrying capacity. However, noise too low to measure means that circuit designers cannot tune the system for optimal performance. The NIST research focuses on CMOS (complementary metal oxide semiconductor) transistors, which are inexpensive and widely used in integrated circuits for wireless devices. Noise levels for CMOS transistors have, until now, been too low to measure accurately in much of their signal frequency range (1 – 10 gigahertz), and as a result CMOS circuits may be poorly matched to wireless transmission systems, resulting in significant signal loss.
In a collaboration with IBM Semiconductor Research and Development Center (Essex Junction, Vt.) and RF Micro Devices (Scotts Valley, Calif.), NIST has developed and demonstrated the capability to reliably measure the noise in CMOS devices before they are cut from silicon wafers and packaged. This is believed to be the first method for on-wafer noise measurements directly linked to national standards for thermal noise power. The new measurement methods were described June 12* at the IEEE Radio Frequency Integrated Circuits Symposium in San Francisco.
The team also demonstrated the use of "reverse" noise measurements--focusing on noise emitted from the input of the transistor when incoming signals are reflected and scattered--as a tool for checking overall noise parameters. This method can improve precision, particularly of the optimal impedance properties needed in transistors to minimize noise, the team found. Reverse noise measurements also may help improve modeling of CMOS transistors.
Laura Ost | EurekAlert!
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