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IMEC reports 3 analog to digital converters with record power efficiency

International solid state circuit conference 2008 - San Francisco - California

At yesterday’s International Solid State Circuit Conference, IMEC presents three ultra-low-power analog to digital converters (ADC) with record figures of merit targeting wireless SDR, 60Ghz communication and sensor networks applications. IMEC has submitted patents for the architecture of its SAR (successive approximation), Flash and CABS (comparator-based asynchronous binary-search) ADC families, to make these available for product development for industry through licensing as white box IP. Future research of IMEC targets even faster ADCs with higher resolution at better power efficiency, to answer the need of future wireless communication products.

IMEC improves power efficiency of 7bit 150Msamples/s ADC with factor 22, with a new CABS ADC architecture IMEC developed a two-step 7bit 150MSamples/s ADC with a record figure of merit of 10fJ per conversion step. The innovative CABS ADC architecture consists of a 1bit coarse ADC and digital to analog converter followed by a 6bit sub-ADC. The 6bit sub-convertor consists of a self-clocked (asynchronous) binary tree of comparators with embedded threshold. The input signal is applied in parallel to all comparators as in the case of Flash converters, but only 6 comparators are triggered by the binary search conversion. The power consumption scales linearly with the sampling rate and equals 0.89µW per MHz clock rate resulting in a record figure of merit of 10fJ/conversion step. This is a factor 22 improvement compared to state-of-the-art ADCs with similar number of bits and sampling speed. The ADC was fabricated in 90nm digital CMOS, and occupies less than 250x250µm².

IMEC beats its own record SAR ADC with improved power efficiency and made it noise-robust IMEC realized a 9bit 40MSamples/s fully-dynamic noise-tolerant SAR ADC achieving a record figure of merit of 54fJ/conversion step. This figure of merit is a 16% improvement compared to IMEC’s last year’s record design presented at ISSCC. That ADC was the world-first charged-based SAR ADC which uses charge-domain signal processing to overcome the fundamental power bottlenecks in successive approximation ADCs. The new design is optimized with an improved sample-and-hold and a noise-robust approach by leveraging redundancy in the search algorithm.The ADC was fabricated in 90nm digital CMOS and occupies less than 220x410µm². Measurements on silicon show a DNL and INL of respectively 0.7/-0.45 and 0.56/-0.65 LSB.

IMEC achieves 3 times better figure of merit for Flash ADC with sampling speed above 500MSamples/s IMEC realized a 5bit 1.75Gsamples/s folding Flash ADC in 90nm digital CMOS with a record figure of merit of 50fJ per conversion step. This is 3 times better compared to the best ever reported converters with sampling speeds over 500Msamples/s.

Flash ADCs are typically used for high-speed applications. In this design, the fundamental power and area limits of Flash ADCs are overcome by using a factor 2 folding technique with only dynamic power consumption and without using amplifiers. In this way, the number of comparators could be reduced from 31 to 16 for a 5 bit resolution.

This folding Flash ADC was fabricated in 90nm digital CMOS, and occupies less than 110x150µm². Measurements at 1.75GSamples/s with a LSB (least significant bit) size of 25mV show an INL (integral non-linearity) and DNL (differential non-linearity) between -0.28/+0.24 and -0.29/+0.26 LSB respectively.

Katrien Marent | alfa
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