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First >100 Mbps mobile SDR baseband platform in processing

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12.02.2008

IMEC has completed design and tape-out of a flexible-air-interface (FLAI) baseband platform for software-defined radios (SDR). IMEC’s solution is to support upcoming generations of mobile devices featuring 802.11n, 802.16e, mobile TV and 3GPP-LTE communication standards. The system-on-chip (SoC) platform and its patented components with their programming environment will be licensed to industry for commercial product development as white-box intellectual property (IP).

The FLAI platform incorporates two IMEC-proprietary ADRES (architecture for dynamically reconfigurable embedded systems) baseband processors fully supported by a proprietary C-code compiler, three digital front-end tiles with a proprietary ASIP (application-specific integrated processor) to assure sync-detection, an ARM™9 processor, and optimized AMBA™ interconnect to link the SoC’s modules with on-chip memories. The IP blocks come with reference platform control software and reference firmware for IEEE802.11n, 802.16e and 3GPP-LTE, as well as integration support.

Thanks to a patented platform control and power management approach, the SoC consumes only a few milliwatts in standby mode, yet is still capable of receiving an immediate burst from any supported wireless standard (reactive radio). When transmitting or receiving data bursts with multi-antenna encoding at more than 100Mbps, platform peak power is only 300mW.

IMEC also expects to combine its FLAI platform and flexible radio front-end (SCALDIO) in order to demonstrate a fully operational software-defined radio later this year. This platform achievement will be followed by a new generation of SDR research results, focusing on SDR and cognitive radio now under development. This new generation also includes a unified application-specific processor architecture that can reduce the area cost of implementing multi-mode advanced forward error correction.

FLAI Specifications

•38 mm² die area
•4 power domains, 8 clocks
•270 I/O pins
•6.7 Mb memory (121 instances)
•2 FLAI-ADRES processors, each with
•33 memory macro @ 400MHz
•32KB instruction cache
•128-entries config mem
•64KB data scratchpad
•128KB IMEM @ 200MHz
•400MHz WCC Clock rate
•25,6GOPS

Katrien Marent | Source: alphagalileo
Further information: www.imec.be/wwwinter/mediacenter/en/SDR_2008.shtml

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